SI4468-7 Datasheet, PDF (29/57 Pages) Silicon Laboratories – Highly configurable packet handler

Si4468/7
5.2. RX Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the
digital domain, which allows for flexibility in optimizing the device for particular applications. The digital modem
performs the following functions:
Channel selection filter
TX modulation
RX demodulation
Automatic Gain Control (AGC)
Preamble detection
Invalid preamble detection
Radio signal strength indicator (RSSI)
Automatic frequency compensation (AFC)
Image Rejection Calibration
Packet handling
Cyclic redundancy check (CRC)
Phase samples output
The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly
configurable. Supported modulation types are GFSK, FSK, 4GFSK, 4FSK, GMSK, and OOK. The channel filter
can be configured to support bandwidths ranging from 850 kHz down to 200 Hz. A large variety of data rates are
supported ranging from 100 bps up to 1 Mbps. The configurable preamble detector is used with the synchronous
demodulator to improve the reliability of the sync-word detection. Preamble detection can be skipped using only
sync detection, which is a valuable feature in some applications. The received signal strength indicator (RSSI)
provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This
high-resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier
sense (CS), and listen before talk (LBT) functionality. A comprehensive programmable packet handler is integrated
to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The
extensive programmability of the packet header allows for advanced packet filtering, which, in turn enables a mix of
broadcast, group, and point-to-point communication. A wireless communication channel can be corrupted by noise
and interference, so it is important to know if the received data is free of errors. A cyclic redundancy check (CRC)
is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of
each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler
and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper
microcontroller. The digital modem includes the TX modulator, which converts the TX data bits into the
corresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta
modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian
filter is implemented to support GFSK and 4GFSK, considerably reducing the energy in adjacent channels. The
default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values.
5.2.1. Ultra Narrow Band (Long Range) Support
The device is capable of supporting ultra-narrow bandwidths down to 200 Hz in all supported frequency bands.
This is implemented by narrowing down the receive channel filter bandwidth in the device and can significantly
improve link budget with a sensitivity of –133 dBm at 100 bps using 2GFSK modulation. These ultra-narrow
bandwidths are useful for applications that need to transmit very small amounts of data, such as status information,
over a very long range. Combined with standby current of 40 nA and transmit current of 18 mA at 10 dBm, a
long-range, low-power solution can be achieved using the widely deployed and field-proven 2GFSK modulation.
The range can be extended further by deploying the 20 dBm PA where the link budget would total 155 dB. A
fast-scanning AFC is supported by using the frequency hop search feature, which alleviates the tolerance
requirements of the crystal or TCXO.
5.2.2. Automatic Gain Control (AGC)
The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The
AGC occurs within a single bit or in less than 2 µs. Peak detectors at the output of the LNA and PGA allow for
optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity performance.
Rev 1.0
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