SI4468-7 Datasheet, PDF (34/57 Pages) Silicon Laboratories – Highly configurable packet handler

Si4468/7
Table 15. Ramp Times as a Function of TC[3:0] Value
TC
Ramp Time (µs)
0
1.25
1
1.33
2
1.43
3
1.54
4
1.67
5
1.82
6
2.00
7
2.22
8
2.50
9
2.86
10
3.33
11
4.00
12
5.00
13
6.67
14
10.00
15
20.00
The ramping profile is close to a linear ramping profile with smoothed out corner when approaching Vhi and Vlo.
The TXRAMP pin can source up to 1 mA without voltage drooping. The TXRAMP pin’s sinking capability is
equivalent to a 10 k pull-down resistor.
Vhi = 3 V when Vdd > 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be
smaller also.
Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10uA need to be sunk into the chip, Vlo will be
10 µA x 10k = 100 mV.
Number
0x2200
0x2201
0x2202
0x2203
Command
PA_MODE
PA_PWR_LVL
PA_BIAS_CLKDUTY
PA_TC
Summary
Sets PA type.
Adjust TX power in fine steps.
Adjust TX power in coarse steps
and optimizes for different
match configurations.
Changes the ramp up/down time
of the PA.
34
Rev 1.0