SI4468-7 Datasheet, PDF (31/57 Pages) Silicon Laboratories – Highly configurable packet handler

Si4468/7
5.2.6. RSSI Jump Indicator (Collision Detection)
The chip is capable of detecting a jump in RSSI in either direction (i.e., either a signal increase or a signal
decrease). Both polarities of jump detection may be enabled simultaneously, resulting in detection of a Jump-Up or
Jump-Down event. This may be used to detect whether a secondary interfering signal (desired or undesired) has
“collided” with reception of the current packet. An interrupt flag or GPIO pin may be configured to notify the host
MCU of the Jump event. The change in RSSI level required to trigger the Jump event is programmable through the
MODEM_RSSI_JUMP_THRESH API property.
The chip may be configured to reset the RX state machine upon detection of an RSSI Jump, and thus to
automatically begin reacquisition of the packet. The chip may also be configured to generate an interrupt.
This functionality is intended to detect an abrupt change in RSSI level and to not respond to a slow, gradual change
in RSSI level. This is accomplished by comparing the difference in RSSI level over a programmable time period. In
this fashion, the chip effectively evaluates the slope of the change in RSSI level.
The arrival of a desired packet (i.e., the transition from receiving noise to receiving a valid signal) will likely be
detected as an RSSI Jump event. For this reason, it is recommended to enable this feature in mid-packet (i.e., after
signal qualification, such as PREAMBLE_VALID.) Refer to the API documentation for configuration options.
5.2.7. Phase Samples Output
To support proprietary demodulation schemes that require phase information, the device can provide phase
samples in the form of a signed 8-bit value over the SPI interface. The radio generates a FIFO almost-full interrupt
based on a user-defined FIFO threshold setting to indicate that phase samples are available. The effective data
rate supported is limited by the SPI interface and the internal sample clock rate. The packet handler cannot be
used simultaneously with this feature as the phase information is loaded into the RX FIFO. A majority of these
applications are expected to use extremely low data rates. The host would need to further process the phase
samples.
5.3. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over the bands from 142–175,
283–350, 350–525, and 850–1050 MHz. Using a  synthesizer has many advantages; it provides flexibility in
choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly
to the loop in the digital domain through the fractional divider, which results in very precise accuracy and control
over the transmit deviation. The frequency resolution in the 850–1050 MHz band is 28.6 Hz with finer resolution in
the other bands. The nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to
32 MHz may be used. The modem configuration calculator in WDS will automatically account for the XTAL
frequency being used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the
VCO is followed by a configurable divider, which will divide the signal down to the desired output frequency band.
5.3.1. Synthesizer Frequency Control
The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will
automatically provide these settings, but the synthesizer equation is shown below for convenience. The APIs for
setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and
FREQ_CONTROL_FRAC0.
RF_channel
=


fc_inte
+
-^f-^c---_{2_}----^f₁-^r-₉-^a---^c--_
 ²-----^-_o----_uf--^r--_te--_d-^q---_i-^_v---^x---^o--Hz
Note: The fc_frac/2¹⁹ value in the above formula has to be a number between 1 and 2.
Rev 1.0
31