SI4468-7 Datasheet, PDF (48/57 Pages) Silicon Laboratories – Highly configurable packet handler

Si4468/7
11. Pin Descriptions: Si4468/7
SDN 1 ^{20 19 18 17} 16
RXp 2
15 nSEL
RXn 3
TX 4
GND
PAD
14 SDI
13 SDO
NC 5
12 SCLK
6 _{7 8 9 10} 11 nIRQ
Pin Pin Name
1
SDN
2
RXp
3
RXn
I/0
Description
Shutdown Input Pin.
I
0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode.
When SDN = 1, the chip will be completely shut down, and the contents of the
registers will be lost.
I _{Differential RF Input Pins of the LNA.}
I ^{See application schematic for example matching network.}
4
TX
5
NC
Transmit Output Pin.
O _{The PA output is an open-drain connection, so the L-C match must supply}
VDD (+3.3 VDC nominal) to this pin.
It is recommended to connect to GND per the reference design schematic. Not
connected internally to any circuitry.
6
VDD
VDD
+1.8 to +3.8 V Supply Voltage Input to Internal Regulators.
The recommended VDD supply voltage is +3.3 V.
7
TXRAMP
O
Programmable Bias Output with Ramp Capability for External FET PA.
See "5.4. Transmitter (TX)" on page 33.
8
VDD
VDD
+1.8 to +3.8 V Supply Voltage Input to Internal Regulators.
The recommended VDD supply voltage is +3.3 V.
9
GPIO0
10
GPIO1
I/O General Purpose Digital I/O.
May be configured through the registers to perform various functions including:
I/O ^{Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery}
Detect, TRSW, AntDiversity control, etc.
11
nIRQ
General Microcontroller Interrupt Status Output.
When the Si446X exhibits any one of the interrupt events, the nIRQ pin will be
O _{set low = 0. The Microcontroller can then determine the state of the interrupt}
by reading the interrupt status. No external resistor pull-up is required, but it
may be desirable if multiple interrupt lines are connected.
48
Rev 1.0