SI53311 Datasheet, PDF(3/30 Page) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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SI53311 Datasheet, PDF (3/30 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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Si53311

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Ambient Operating

Temperature

Symbol

Test Condition

Min

Typ

Max Unit

â40

Â°C

Supply Voltage Range*

VDD

LVDS, CML, HCSL, LVCMOS

1.71

1.8

1.89 V

LVPECL, low power LVPECL,

2.38

2.5

2.63 V

LVDS, CML, HCSL, LVCMOS

2.97

3.3

3.63 V

Output Buffer Supply

Voltage*

VDDO

LVDS, CML, HCSL, LVCMOS

1.71

1.89 V

LVPECL, low power LVPECL,

2.38

2.63 V

LVDS, CML, HCSL, LVCMOS

2.97

3.63 V

*Note: Core supply VDD and output buffer supplies VDDO are independent.

Table 2. Input Clock Specifications

(VDD=1.8 V ï± 5%, 2.5 V ï± 5%, or 3.3 V ï± 10%, TA=â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Differential Input Common

VCM

VDD = 2.5 Vï± 5%, 3.3 Vï± 10%

0.05

Mode Voltage

Input Swing

VIN

(single-ended, peak-to-

peak)

0.1

Input Voltage High

VIH

VDD x

0.7

Max Unit

1.1

Input Voltage Low

VIL

VDD x V

0.3

Input Capacitance

CIN

Preliminary Rev. 0.4

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