SI53311 Datasheet, PDF (13/30 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53311
2.4. Input Mux and Output Enable Logic
The Si53311 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 15. Input Mux and Output Enable Logic
CLK_SEL CLK0
CLK1
OE¹
Q²
L
L
X
H
L
L
H
X
H
H
H
X
L
H
L
H
X
H
H
H
X
X
X
L
L³
Notes:
1. Output enable active high
2. On the next negative transition of CLK0 or CLK1.
3. Single-end: Q=low, Q=high
Differential: Q=low, Q=high
2.5. Flexible Output Divider
The Si53311 provides optional clock division in addition to clock distribution. The divider setting for each bank of
output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVX pins open will force
a divider value of 1 which is the default mode of operation.
Table 16. Divider Selection
DIVX
Open*
Divider Value
1 (default)
0
2
1
4
*Note: DIVX are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to
V_DD/2.
Preliminary Rev. 0.4
13