SI53311 Datasheet, PDF (1/30 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53311
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ)
Features
 6 differential or 12 LVCMOS outputs  Low output-output skew: <50 ps
 Ultra-low additive jitter: 100 fs rms  Low propagation delay variation:
 Wide frequency range:
<400 ps
1 MHz to 1.25 GHz
 Independent V_DD and V_DDO :
 Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, Low Power _{ Excellent power supply noise}
LVPECL, LVDS, CML, HCSL,
rejection (PSRR)
LVCMOS
 Selectable LVCMOS drive strength to
 2:1 mux with hot-swappable inputs
tailor jitter and EMI performance
 Asynchronous output enable
 Output clock division: /1, /2, /4
 Small size: 32-QFN (5 mm x 5 mm)
 RoHS compliant, Pb-free
 Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 25.
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53311 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53311 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53311 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53311 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Pin Assignments
Si53311
DIVA 1
SFOUTA[1] ²
SFOUTA[0] 3
Q0 ⁴
Q0 5
GND ⁶
VDD
7
CLK_SEL 8
GND
PAD
24 DIVB
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 _VDDOB
18 V_DDOA
17 _VREF
Patents pending
Functional Block Diagram
VREF
Vref
Generator
Power
Supply
Filtering
CLK0
CLK0
CLK1
CLK1
CLK_SEL
DivA
DivB
Switching
Logic
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2
Q0, Q1, Q2
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q3, Q4, Q5
Q3, Q4, Q5
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53311
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.