SI53311 Datasheet, PDF (23/30 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53311
Table 20. Pin Description (Continued)
Pin
Name
Description
8
CLK_SEL
Mux input select pin (LVCMOS)
Clock inputs are switched without the introduction of glitches.
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
9
NC
No connect.
10
CLK0
Input clock 0
11
CLK0
Input clock 0 (complement)
When the CLK0 is driven by a single-end input, connect V_REF to CLK0.
CLK0 contains an internal pull-up resistor.
12
OEA
Output enable—Bank A
When OE=high, the Bank A outputs are enabled.
When OE=low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OEA contains an internal pull-up resistor.
13
OEB
Output enable—Bank B
When OE=high, the Bank B outputs are enabled.
When OE=low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OEB contains an internal pull-up resistor.
14
CLK1
Input clock 1
15
CLK1
Input clock 1 (complement)
When the CLK1 is driven by a single-end input, connect V_REF to CLK1.
CLK1 contains an internal pull-up resistor.
16
NC
No connect.
17
V_REF
Input reference voltage
When driven by a LVCMOS clock input, connect the unused clock input to V_REF and
a 0.1µF cap to ground. When driven by a differential clock, do not connect the V_REF
pin.
18
V_DDOA
Output voltage supply—Bank A (Outputs: Q0 to Q2)
Bypass with 1.0 F capacitor and place as close to the V_DDOA pin as
possible.
19
V_DDOB
Output voltage supply—Bank B (Outputs: Q3 to Q5)
Bypass with 1.0 F capacitor and place as close to the V_DDOB pin as
possible.
20
Q5
Output clock 5 (complement)
21
Q5
Output clock 5
Preliminary Rev. 0.4
23