SI53311 Datasheet, PDF (24/30 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53311
Pin
22
23
24
25
26
27
28
29
30
31
32
GND
Pad
Name
SFOUTB[0]
SFOUTB[1]
DIVB
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
GND
Table 20. Pin Description (Continued)
Description
Output signal format control pin for Bank B.
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output signal format control pin for Bank B.
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output divider configuration bit for Bank B.
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output clock 4 (complement)
Output clock 4
Output clock 3 (complement)
Output clock 3
Output clock 2 (complement)
Output clock 2
Output clock 1 (complement)
Output clock 1
Ground Pad.
Power supply ground and thermal relief.
24
Preliminary Rev. 0.4