SI53311 Datasheet, PDF (21/30 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53311
2.12. Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low
jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and
SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply
Rejection for Low Jitter Clocks.”




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Figure 11. Power Supply Noise Rejection (100mVpp Sinusoidal Power Supply Noise Applied)
Preliminary Rev. 0.4
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