SI5013 Datasheet, PDF (24/26 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 1.0
Added Figure 4, “PLL Acquisition Time,” on page 6.
Table 2 on page 7
Updated values: Supply Current
Updated values: Power Dissipation
Updated values: Common Mode Input Voltage
(REFCLK)
Updated values: Output Common Mode Voltage
Table 3 on page 8
Updated values: Output Clock Rise Time
Updated values: Output Clock Fall Time
Updated values: Clock to Data Delay t_Cf-D
Table 4 on page 9
Updated values: Jitter Tolerance (OC-12)
Updated values: RMS Jitter Generation
Updated values: Peak-to-Peak Jitter Generation
Updated values: Acquisition Time (reference clock
applied)
Updated values: Acquisition Time
(reference-less operation)
Updated values: Freq Difference at which Receive PLL
goes out of Lock
Updated values: Freq Difference at which Receive PLL
goes into Lock
Removed “Hysteresis Dependency” Figure.
Added Figure 7, “LOS Signal Hysteresis,” on page
13.
Corrected error: Table 8 on page 19—changed
description for LOS_LVL from “LOS is disabled when
the voltage applied is less than 500 mV” to “LOS is
disabled when the voltage applied is less than
1.0 V.”
Revision 1.0 to Revision 1.1
Corrected “Revision 0.2 to Revision 1.0” Change
List.
Table 4 on page 9
Updated values: Jitter Tolerance (OC-3)
Revision 1.1 to Revision 1.2
Added Figure 5, “LOS Response,” on page 6.
Updated Table 2 on page 7.
Added “Output Common Mode Voltage (DOUT)” with
updated values.
Added “Output Common Mode Voltage (CLKOUT)” with
updated values.
Updated Table 3 on page 8.
Added “Output Clock Duty Cycle—OC-12/3.”
Added “Loss-of-Signal Response Time” with updated
values.
Updated Table 8 on page 19.
Changed “clock input” to “DIN inputs” for Loss Of Signal
Updated Figure 16, “28-Lead Quad Flat No-Lead
(QFN),” on page 23.
Updated Table 9, “Package Diagram Dimensions,”
on page 23.
Changed dimension A.
Changed dimension E2.
Revision 1.2 to Revision 1.3
Updated Figure 16, “28-Lead Quad Flat No-Lead
(QFN),” on page 23.
Updated Table 9, “Package Diagram Dimensions,”
on page 23.
Revision 1.3 to Revision 1.4
Updated "Features" on page 1.
Table 2 on page 7.
Updated supply current values.
Updated power dissipation values.
Updated differential output voltage swing
(DOUT and CLKOUT).
Table 3 on page 8.
Added output clock rate values.
Updated duty cycle values.
Updated slice accuracy values.
Table 4 on page 9.
Updated jitter tolerance values (OC-12 mode).
Updated acquisition time values.
Updated reference clocks range.
Updated reference clocks tolerance.
"3.Typical Application Schematic" on page 11.
Added 1% to Rext.
"4.11.PLL Performance" on page 14.
Removed OC-24 note.
Table 8 on page 19.
Added no-hysteresis text to BER_LVL.
Updated "6.Ordering Guide" on page 22.
Added “X” to part number.
Revision 1.4 to Revision 1.5
Updated Table 2 on page 7.
Added limits for V_ICM.
Updated V_OD.
Updated Table 3 on page 8.
Updated T_Cr-D.
Updated T_Cf-D.
Revised SLICE specification.
Updated "4.8.Loss-of-Signal (LOS)" on page 13.
24
Rev. 1.5