SI5013 Datasheet, PDF (21/26 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
Pin #
16
17
19
20
22
23
24
26
27
28
GND Pad, 2
Table 8. Si5013 Pin Descriptions (Continued)
Pin Name
DOUT–
DOUT+
RESET/CAL
REXT
CLKOUT–
CLKOUT+
CLKDSBL
BER_LVL
BER_ALM
NC
GND
I/O Signal Level
Description
O
CML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN.
I
LVTTL Reset/Calibrate.
Driving this input high for at least 1 µs will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low.
Note: This input has a weak internal pulldown.
External Bias Resistor.
This resistor is used to establish internal bias cur-
rents within the device. This pin must be connected
to GND through a 10 kΩ (1%) resistor.
O
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
I
LVTTL Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pulldown.
I
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. When the BER exceeds the pro-
grammed threshold, BER_ALM is driven low. If this
pin is tied to GND, BER_ALM is disabled. There is
no hysteresis.
O
LVTTL Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded. The
alarm will clear after the BER rate has improved by
approximately a factor of 2.
No Connect.
Leave this pin disconnected.
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 28-lead QFN (see Figure 16 on page 23)
must be connected directly to supply ground. Min-
imize the ground path inductance for optimal perfor-
mance.
Rev. 1.5
21