SI5013 Datasheet, PDF (14/26 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
LOS signal hysteresis for the Si5013 CDR. The value of
R1 may be chosen to provide a range of hysteresis from
3 to 8 dB where a nominal value of 800 Ω adjusts the
hysteresis level to approximately 6 dB. Use a value of
500 Ω or 1000 Ω for R1 to provide 3 dB or 8 dB of
hysteresis, respectively.
Hysteresis is defined as the ratio of the LOS deassert
level (LOSD) and the LOS assert level (LOSA). The
hysteresis in decibels is calculated as 20log(LOSD/
LOSA).
4.9. Bit Error Rate (BER) Detection
The Si5013 uses a proprietary Silicon Laboratories
algorithm to generate a bit-error-rate (BER) alarm on
the BER_ALM pin if the observed BER is greater than a
user programmable threshold. Bit error detection relies
on the input data edge timing; edges occurring outside
of the expected event window are counted as bit errors.
The BER threshold is programmed by applying a
voltage to the BER_LVL pin between 500 mV and
2.25 V corresponding to a BER of approximately 10–10
and 10–6, respectively. The voltage present on
BER_LVL maps to the BER as follows: log10(BER) = (4
x BER_LVL) – 13. (BER_LVL is in volts; BER is in bits
per second.).
4.10. Data Slicing Level
The Si5013 provides the ability to externally adjust the
slicing level for applications that require bit error rate
(BER) optimization. Adjustments in slicing level of
±15 mV (typical, relative to the internally set input
common mode voltage) are supported. The slicing level
is set by applying a voltage between 0.75 and 2.25 V to
the SLICE_LVL input. See Figure 8 for the operation
levels of the slice circuit.
When SLICE_LVL is driven below 500 mV, the slicing
level adjustment is disabled, and the slicing level is set
to the cross-point of the differential input signal.
Note: The slice circuit is designed to only work with pseudo-
random, dc-balanced data.
4.11. PLL Performance
The PLL implementation used in the Si5013 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
4.11.1. Jitter Tolerance
The Si5013’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 8. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
25
20
15
10
5
0
-5
-10
-15
-20
-25
0.00
0.25
0.50
Upper Limit
Typical
Lower Limit
0.75
1.00
10 mV
10 mV
Note: SLICE is a continuous curve. This chart shows
the range of results from part-to-part.
1.25
1.50
1.75
2.00
2.25
Figure 8. OC-12 and OC-3 Slice Specification
14
Rev. 1.5