SI5013 Datasheet, PDF (1/26 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
Features
High-speed clock and data recovery device with integrated limiting amplifier:
Supports OC-12/3, STM-4/1
Loss-of-signal level alarm
DSPLL^® technology
Jitter generation 2.3 mUI_rms (typ)
Small footprint: 5 x 5 mm
Data slicing level control
10 mV_PP differential sensitivity
3.3 V supply
Reference and reference-less
operation supported
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Description
The Si5013 is a fully-integrated, high-performance limiting amplifier (LA)
and clock and data recovery (CDR) IC for high-speed serial
communication systems. It derives timing information and data from a
serial input at OC-12/3 and STM-4/1 rates. Use of an external reference
clock is optional. Silicon Laboratories DSPLL^® technology eliminates
sensitive noise entry points, thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
The Si5013 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
Ordering Information:
See page 22.
Pin Assignments
Si5013
28 27 26 25 24 23 22
RATESEL 1
21 VDD
GND 2
20 REXT
LOS_LVL 3
SLICE_LVL 4
REFCLK+ 5
GND
Pad
19 RESET/CAL
18 VDD
17 DOUT+
REFCLK– 6
16 DOUT–
LOL 7
15 TDI
8 9 10 11 12 13 14
LOS_LVL
LOS
DIN+
DIN–
REFCLK+
REFCLK–
(Optional)
Signal
Detect
Retimer
2
BUF
2
Limiting
Amp
DSPLL
BER
Monitor
2
BUF
2
Lock
Detection
Bias Gen.
Reset/
Calibration
SLICE_LVL
BER_ALM
REXT
LTR ^BER_LVL
LOL ^RATESEL
RESET/CAL
DSQLCH
DOUT+
DOUT–
CLKOUT+
CLKOUT–
CLK_DSBL
Rev. 1.5 10/05
Copyright © 2005 by Silicon Laboratories
Si5013