SI5320 Datasheet, PDF (21/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

2.13. Design and Layout Guidelines
Precision clock circuits are susceptible to board noise
and EMI. To take precautions against unacceptable
levels of board noise and EMI affecting performance of
the Si5320, consider the following:
 Power the device from 3.3 V since the internal
regulator provides at least 40 dB of isolation to the
V_DD25 pins (which power the PLL circuitry).
 Use an isolated local plane to connect the V_DD25
pins. Avoid running signal traces over or below this
plane without a ground plane in between.
 Route all I/O traces between ground planes as much
as possible
 Maintain an input clock amplitude in the 200 mV_PP to
500 mV_PP differential range.
 Excessive high-frequency harmonics of the input
clock should be minimized. The use of filters on the
input clock signal can be used to remove high-
frequency harmonics.
Si5320
Rev. 2.5
21