SI5320 Datasheet, PDF (10/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V_DD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
J_TOL(PP)
f = 16 Hz
f = 160 Hz
1000 —
100 —
— ns
— ns
f = 1600 Hz
10 — — ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00
J_GEN(RMS)
12 kHz to 20 MHz
50 kHz to 80 MHz
— 0.82 1.0 ps
— 0.26 0.35 ps
CLKOUT RMS Jitter Generation
FEC[1:0] = 01, 10
J_GEN(RMS)
12 kHz to 20 MHz
50 kHz to 80 MHz
— 0.79 1.0 ps
— 0.26 0.35 ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00
J_GEN(PP)
12 kHz to 20 MHz
50 kHz to 80 MHz
— 7.3 10.0 ps
— 3.8 5.0 ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 01, 10
J_GEN(PP)
12 kHz to 20 MHz
50 kHz to 80 MHz
— 7.1 10.0 ps
— 4.3 5.0 ps
Jitter Transfer Bandwidth (see Figure 10)
F_BW
BW = 1600 Hz
— 1600 — Hz
Wander/Jitter Transfer Peaking
J_P
< 1600 Hz
— 0.0 0.1 dB
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
f = 32 Hz
500 — — ns
f = 320 Hz
50 — — ns
f = 3200 Hz
5 — — ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00
J_GEN(RMS)
12 kHz to 20 MHz
50 kHz to 80 MHz
— 0.72 0.9 ps
— 0.24 0.3 ps
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of
nanoseconds per millisecond. The equivalent ps/s unit is used here since the maximum phase transient magnitude for the
Si5320 (tPT_MTIE) never reaches one nanosecond.
10
Rev. 2.5