SI5320 Datasheet, PDF (17/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
Table 7. Loop Bandwidth Settings
Loop Bandwidth BWSEL1 BWSEL0 DBLBW^*
12800 Hz
1
1
1
6400 Hz
1
1
0
6400 Hz
0
0
1
3200 Hz
0
0
0
3200 Hz
0
1
1
1600 Hz
0
1
0
1600 Hz
1
0
1
800 Hz
1
0
0
*Note: When DBLBW = 1, FXDDELAY must be asserted and
FEC scaling must be disabled.
Table 8. Nominal Clock Input Frequencies
Input Clock
Frequency
Range
Reserved
622 MHz
311 MHz
155 MHz
77 MHz
38 MHz
19 MHz
Reserved
INFRQSEL2 INFRQSEL1 INFRQSEL0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Table 9. Nominal Clock Output Frequencies
Output Clock Frequency
Range
622 MHz
155 MHz
19 MHz
Driver Powerdown
FRQSEL1 FRQSEL0
1
1
1
0
0
1
0
0
Table 10. FEC Frequency Scalings
FEC Frequency
Scaling
1/1
255/238
238/255
Reserved
FEC1
0
0
1
1
FEC0
0
1
0
1
2.2.1. FEC Rate Conversion
The Si5320 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, or 32x clock frequency multiplication
function with an option for additional frequency scaling
by a factor of 255/238 or 238/255 for FEC rate
compatibility. The multiplication factor is configured by
selecting the input and output clock frequency ranges
for the device. The additional frequency scaling by a
factor of either 255/238 or 238/255 for FEC compatibility
is selected using the FEC[1:0] control inputs. (See
Table 10.)
For example, a 622.08 MHz output clock (a non-FEC
rate) can be generated from a 19.44 MHz input clock (a
non-FEC rate) by setting INFRQSEL[2:0] = 001
(19.44 MHz range), setting FRQSEL [1:0] = 11 (32x
multiplication), and setting FEC[1:0] = 00 (no FEC
scaling).
A 666.51 MHz output clock (a FEC rate) can be
generated from a 19.44 MHz input clock (a non-FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL [1:0] = 11 (32x multiplication),
and setting FEC[1:0] = 01 (255/238 FEC scaling).
Finally, a 622.08 MHz output clock (a non-FEC rate) can
be generated from a 20.83 MHz input clock (a FEC rate)
by setting INFRQSEL[2:0] = 001 (19.44 MHz range),
setting FRQSEL [1:0] = 11 (32x multiplication), and
setting FEC[1:0] = 10 (238/255 FEC scaling).
2.3. PLL Performance
The Si5320 PLL is designed to provide extremely low
jitter generation, high jitter tolerance, and a well-
controlled jitter transfer function with low peaking and a
high degree of jitter attenuation.
2.3.1. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
also a function of the PLL bandwidth setting. Higher
loop bandwidth settings may result in lower jitter
generation, but may also result in less attenuation of
jitter on the input clock signal.
2.3.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5320 provides tightly-
controlled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
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