SI5320 Datasheet, PDF (13/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V_DD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Acquisition Time
T_AQ
RSTN/CAL high to
— 300 350 ms
CAL_ACTV low, with valid
clock input and
VALTIME = 0
Clock Output Wander with
Temperature Gradient ^1,2
C_{CO_TG}
Stable Input Clock;
Temperature
Gradient <10 C/min;
800 Hz Loop BW
— — 50 ps/
C/
min
Initial Frequency Accuracy in Digital Hold
C_{DH_FA}
Mode (first 100 ms with supply voltage and tem-
perature held constant)
Stable Input Clock
Selected until entering
Digital Hold
— — 10 ppm
Clock Output Frequency Accuracy Over
Temperature in Digital Hold Mode
C_{DH_T}
Constant Supply Voltage
— 16.7 30 ppm
/C
Clock Output Frequency Accuracy Over Supply C_{DH_V33}
Voltage in Digital Hold Mode
Constant Temperature
— — 250 ppm
/V
Clock Output Phase Step³ (See Figure 8)
t_{PT_MTIE} When hitlessly recovering —
from Digital Hold mode
1/1
–200 0
200 ps
Clock Output Phase Step Slope³ (See Figure 8)
BWSEL[1:0] = 11, FEC[1:0] = 00, DBLBW = 0
BWSEL[1:0] = 00, FEC[1:0] = 00, DBLBW = 0
BWSEL[1:0] = 01, FEC[1:0] = 00, DBLBW = 0
BWSEL[1:0] = 10, FEC[1:0] = 00, DBLBW = 0
m_PT
When hitlessly recovering
from Digital Hold mode
6400 Hz, No Scaling
—
3200 Hz, No Scaling
—
1600 Hz, No Scaling
—
800 Hz, No Scaling
—
— 10 ps/
— 5 s
— 2.5
— 1.25
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of
nanoseconds per millisecond. The equivalent ps/s unit is used here since the maximum phase transient magnitude for the
Si5320 (tPT_MTIE) never reaches one nanosecond.
Rev. 2.5
13