SI8605 Datasheet, PDF (17/40 Pages) Silicon Laboratories – BIDIRECTIONAL IC ISOLATORS WITH UNIDIRECTIONAL DIGITAL CHANNELS

Si860x
3.3. I²C Isolator Design Constraints
Table 13 lists the I²C isolator design constraints.
Table 13. Design Constraints
Design Constraint
Data Sheet Values
Effect of Bus Pull-up Strength
and Temperature
To prevent the latch condition, the
isolator output low level must be
greater than the isolator input low
level.
Isolator V_OL 0.7 V typical
Isolator V_IL 0.5 V typical
This is normally guaranteed by the
isolator data sheet. However, if the
pull up strength is too weak, the out-
Input/Output Logic Low Level
put low voltage will fall and can get
Difference
too close to the input low logic level.
∆VSDA1, ∆VSCL1 = 50 mV minimum ^{These track over temperature.}
The bus output low must be less
than the isolator input low logic
level.
The isolator output low must be
less than the bus input low.
Bus V_OL = 0.4 V maximum
Isolator V_IL = 0.41 V minimum
If the pull up strength is too large,
the devices on the bus might not pull
the voltage below the input low
range. These have opposite tem-
perature coefficients. Worst case is
hot temperature.
If the pull up strength is too large,
the isolator might not pull below the
Bus V_IL 0.3 x V_DD = 1.0 V minimum for bus input low voltage.
V_DD = 3.3 V
Si8600/02/05/06 Vol: –1.8 mV/C
CMOS buffer: –0.6 mV/C
Isolator V_OL = 0.8 V maximum
This provides some temperature
tracking, but worst case is cold tem-
perature.
3.4. I²C Isolator Design Considerations
The first step in applying an I²C isolator is to choose which side of the bus will be connected to the isolator A side.
Ideally, it should be the side which:
1. Is compatible with the range of bus pull up specified by the manufacturer. For example, the Si8600/02/05/06
isolators are normally used with a pull up of 0.5 mA to 3 mA.
2. Has the highest input low level for devices on the bus. Some devices may specify an input low of 0.9 V and
other devices might require an input low of 0.3 x Vdd. Assuming a 3.3 V minimum power supply, the side with
an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V.
3. Have devices on the bus that can pull down below the isolator input low level. For example, the Si860x input
level is 0.41 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue.
4. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV.
Rev. 1.4
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