SI8605 Datasheet, PDF (16/40 Pages) Silicon Laboratories – BIDIRECTIONAL IC ISOLATORS WITH UNIDIRECTIONAL DIGITAL CHANNELS

Si860x
3. Typical Application Overview
3.1. I²C Background
In many applications, I²C, SMBus, and PMBus interfaces require galvanic isolation for safety or ground loop
elimination. For example, Power over Ethernet (PoE) applications typically use an I²C interface for communication
between the PoE power sourcing device (PSE), and the earth ground referenced system controller. Galvanic
isolation is required both by standard and also as a practical matter to prevent ground loops in Ethernet connected
equipment.
The physical interface consists of two wires: serial data (SDA) and serial clock (SCL). These wires are connected
to open collector drivers that serve as both inputs and outputs. At first glance, it appears that SDA and SCL can be
isolated simply by placing two unidirectional isolators in parallel, and in opposite directions. However, this
technique creates feedback that latches the bus line low when a logic low asserted by either master or slave. This
problem can be remedied by adding anti-latch circuits, but results in a larger and more expensive solution. The
Si860x products offer a single-chip, anti-latch solution to the problem of isolating I²C/SMBus applications and
require no external components except the I²C/SMBus pull-up resistors. In addition, they provide isolation to a
maximum of 5.0 kV_RMS, support I²C clock stretching, and operate to a maximum I²C bus speed of 1.7 Mbps.
3.2. I²C Isolator Operation
Without anti-latch protection, bidirectional I²C isolators latch when an isolator output logic low propagates back
through an adjacent isolator channel creating a stable latched low condition on both sides. Anti-latch protection is
typically added to one side of the isolator to avoid this condition (the “A” side for the Si8600/02/05/06).
The following examples illustrate typical circuit configurations using the Si8600/02/05/06.
I²C/SMBus
Unit 1
V_IL
V_OL
Si8600/02/05/06
+
-
ISO1
V_IL
V_OL
ISO2
I²C/SMBus
Unit 2
Figure 9. Isolated Bus Overview (I²C Channels Only)
The “A side” output low (V_OL) and input low (V_IL) levels are designed such that the isolator V_OL is greater than the
isolator V_IL to prevent the latch condition.
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