SI8431BB-C-IS Datasheet, PDF (14/38 Pages) Silicon Laboratories – LOW-POWER TRIPLE-CHANNEL DIGITAL ISOLATOR

Si8430/31/35
Table 5. Electrical Characteristics¹ (Continued)
(V_DD1 = 2.70 V, V_DD2 = 2.70 V, T_A = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
Si843xBx
Maximum Data Rate
0
Minimum Pulse Width
—
Propagation Delay
t_PHL, t_PLH See Figure 2
3.0
Pulse Width Distortion
|t_PLH - t_PHL|
PWD
See Figure 2
—
Propagation Delay Skew³
t_PSK(P-P)
—
Channel-Channel Skew
t_PSK
—
All Models
—
150 Mbps
—
6.0
ns
6.0
9.5
ns
1.5
2.5
ns
2.0
3.0
ns
0.5
1.8
ns
Output Rise Time
t_r
C_L = 15 pF
See Figure 2
—
4.8
6.5
ns
Output Fall Time
t_f
C_L = 15 pF
See Figure 2
—
3.2
4.6
ns
Common Mode Transient
Immunity
CMTI V_I = V_DD or 0 V
—
25
— kV/µs
Enable to Data Valid⁴
t_en1
See Figure 1
—
5.0
8.0
ns
Enable to Data Tri-State⁴
t_en2
See Figure 1
—
7.0
9.2
ns
Start-up Time^4,5
t_SU
—
15
40
µs
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to T_A = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. t_PSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
14
Rev. 1.5