S-93C46C Datasheet, PDF (9/39 Pages) Seiko Instruments Inc – 3-WIRE SERIAL E2PROM

Rev.1.1_00
3-WIRE SERIAL E²PROM
S-93C46C/56C/66C/76C/86C
 AC Electrical Characteristics
Table 9 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.1 × V_CC to 0.9 × V_CC
0.5 × V_CC
100 pF
Table 10
Item
Symbol
V_CC = 1.6 V to 1.8 V
Min.
Max.
Ta = −40°C to +85°C
V_CC = 1.8 V to 2.5 V V_CC = 2.5 V to 4.5 V V_CC = 4.5 V to 5.5 V Unit
Min.
Max.
Min. Max. Min. Max.
CS pin setup time t_CSS
0.4
−
0.2
−
0.15
−
0.15
−
μs
CS pin hold time
t_CSH
0
−
0
−
0
−
0
−
μs
CS pin deselect time t_CDS
0.4
−
0.2
−
0.2
−
0.2
−
μs
Data setup time
t_DS
0.2
−
0.1
−
0.1
−
0.1
−
μs
Data hold time
t_DH
0.2
−
0.1
−
0.1
−
0.1
−
μs
Output delay time t_PD
Clock frequency^*1
f_SK
SK clock time "L"^*1 t_SKL
SK clock time "H"^*1 t_SKH
−
0.8
−
0.6
−
0.25
−
0.25 μs
0
0.5
0
1.0
0
2.0
0
2.0 MHz
0.5
−
0.2
−
0.2
−
0.1
−
μs
0.5
−
0.2
−
0.2
−
0.1
−
μs
Output disable time t_HZ1, t_HZ2
0
0.5
0
0.2
0
0.2
0
0.15 μs
Output enable time t_SV
0
0.5
0
0.2
0
0.2
0
0.15 μs
Write time
t_PR
−
4.0
−
4.0
−
4.0
−
4.0 ms
*1. The clock cycle of the SK clock (frequency f_SK) is 1/f_SK μs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/f_SK) = t_SKL (min.) + t_SKH (min.) by minimizing
the SK clock cycle time.
t CSS
1/f_SK^*2
t CDS
CS
t SKH
t SKL
t CSH
SK
t DS
t DH
tDS tDH
DI
High-Z^*1
DO
(READ)
t SV
DO ^High-Z
(VERIFY)
Valid data
t PD
t HZ2
Valid data
t PD
High-Z
t HZ1
High-Z
*1. Indicates high impedance.
*2. 1/f_SK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics.
Note that the clock cycle cannot be set as (1/f_SK) = t_SKL (min.) + t_SKH (min.) by minimizing the SK clock cycle
time.
Figure 1 Timing Chart
9