S-93C46C Datasheet, PDF (19/39 Pages) Seiko Instruments Inc – 3-WIRE SERIAL E2PROM

Rev.1.1_00
3-WIRE SERIAL E²PROM
S-93C46C/56C/66C/76C/86C
3. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to "1", change the CS pin to "H", and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no need to
input data. The chip erase operation starts when the CS pin goes to "L". When the clocks more than the specified
number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the clock
pulse monitoring circuit, refer to " Function to Protect Against Write due to Erroneous Instruction
Recognition".
CS
tCDS
Verify
Standby
SK
1
2
34
5
6
7
89
DI
<1> 0
010
4xs
tSV
tHZ1
DO
High-Z
Busy _Ready
High-Z
tPR
Figure 14 Chip Erase Timing (S-93C46C)
CS
tCDS
Verify
Standby
SK
1
2
3
4
5
6
7
8
9 10 11
DI
<1> 0
010
High-Z
DO
6xs
tSV
tHZ1
Busy _Ready
High-Z
t PR
Figure 15 Chip Erase Timing (S-93C56C/66C)
CS
t_CDS
SK
1 2 3 4 5 6 7 8 9 10 11 12 13
Verify
Standby
DI
<1> _{0 0 1 0}
8xs
High-Z
DO
t_SV
t_HZ1
busy _ready
High-Z
t_PR
Figure 16 Chip Erase Timing (S-93C76C/86C)
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