S-1004NA10I-M5T1U Datasheet, PDF (32/42 Pages) Seiko Instruments Inc – Release delay time accuracy

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_01
17. Release delay time (tRESET) vs. Power supply voltage (VDD)
S-1004Cx10
16
Ta = +25°C,
CD = 4.7 nF
15
14
13
12
11
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
VIH^*1
1 s
SENSE pin voltage
VIL^*2
VDD
Output voltage
tRESET
VDD  90%
VSS
*1. VIH = 10 V
*2. VIL = 0.95 V
Figure 36 Test Condition of Release Delay Time
V_DD
P.G.
VDD
SENSE OUT
VSS CD
C_D
R
100 kΩ
Oscilloscope
V_DD
P.G.
VDD
SENSE OUT
VSS CD
C_D
Oscilloscope
Figure 37 Test Circuit of Release Delay Time
(Nch open-drain output product)
Figure 38 Test Circuit of Release Delay Time
(CMOS output product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
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