S-1004NA10I-M5T1U Datasheet, PDF (16/42 Pages) Seiko Instruments Inc – Release delay time accuracy

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_01
 Operation
1. Basic operation
1. 1 S-1004 Series NA / NB type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (+VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up. Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB +
RA
RC ) • VSENSE
+ RB + RC
.
(2) Even if VSENSE decreases to +VDET or lower, VDD is output when VSENSE is higher than the detection voltage
(−VDET).
When VSENSE decreases to −VDET or lower (point A in Figure 23), the Nch transistor is turned on. And then VSS
("L") is output from the OUT pin after the elapse of the detection delay time (tDET).
At this time, N1 is turned on, and the input voltage to the comparator is
RB •
RA
VSENSE
+ RB
.
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds −VDET, VSS is output when VSENSE is lower than +VDET.
(5) When VSENSE increases to +VDET or higher (point B in Figure 23), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tRESET) when the output is pulled up.
VDD
V_DD
V_SENSE
VSS
SENSE
R_A
*1
*1
R_B
V_REF
R_C
+
−
N1
Delay
circuit
Nch
*1
OUT
R
100 kΩ
*1
+
V
CD
C_D
*1. Parasitic diode
Figure 22 Operation of S-1004 Series NA / NB Type
(1) (2) (3) (4) (5)
Hysteresis width
(V_HYS)
A
V_SENSE
B
Release voltage (+V_DET)
Detection voltage (−V_DET)
Minimum operation voltage
V_SS
V_DD
Output from OUT pin
V_SS
t_DET
t_RESET
Figure 23 Timing Chart of S-1004 Series NA / NB Type
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