S-1004NA10I-M5T1U Datasheet, PDF (11/42 Pages) Seiko Instruments Inc – Release delay time accuracy

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_01
S-1004 Series
2. CMOS output product
Item
Symbol
Table 12
Condition
(Ta = +25°C unless otherwise specified)
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage^*1 −VDET
0.95 V ≤ VDD ≤ 10.0 V
1.0 V ≤ −VDET(S) < 2.2 V
2.2 V ≤ −VDET(S) ≤ 5.0 V
−VDET(S)
− 0.022
−VDET(S)
× 0.99
−VDET(S)
−VDET(S)
−VDET(S)
+ 0.022
−VDET(S)
× 1.01
V
V
1
1
Hysteresis width VHYS
−
−VDET −VDET −VDET
× 0.03 × 0.05 × 0.07
V
1
Current
consumption^*2
ISS
VDD = 10.0 V, VSENSE = −VDET(S) + 1.0 V
−
0.50 0.90 μA
2
Operation voltage VDD
−
0.95
−
10.0
V
1
Output transistor
VDD = 0.95 V
0.59 1.00
−
mA
3
Output current
IOUT
Nch
VDS^*3 = 0.5 V
VSENSE = 0.0 V
Output transistor
Pch
VDD = 1.2 V
VDD = 2.4 V
VDD = 4.8 V
VDD = 4.8 V
0.73 1.33
−
mA
3
1.47 2.39
−
mA
3
1.86 2.50
−
mA
3
1.62 2.60
−
mA
5
VDS^*3 = 0.5 V
VSENSE = 10.0 V
VDD = 6.0 V
1.78 2.86
−
mA
5
Detection voltage
temperature
coefficient^*4
Δ−VDET
ΔTa • −VDET
Ta
=
−40°C
to
+85°C
−
±100 ±350 ppm/°C 1
Detection
delay time^*5
tDET
VDD = 5.0 V
−
40
−
μs
4
Release
delay time^*6
tRESET
VDD = −VDET(S) + 1.0 V, CD = 4.7 nF
10.79 12.69 14.59 ms
4
SENSE pin
resistance
RSENSE
1.0 V ≤ −VDET(S) < 1.2 V
1.2 V ≤ −VDET(S) ≤ 5.0 V
5.0
19.0 42.0 MΩ
2
6.0
30.0 98.0 MΩ
2
*1. −VDET: Actual detection voltage value, −VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 5 or Table 6)
*2. The current flowing through the SENSE pin resistance is not included.
*3. VDS: Drain-to-source voltage of the output transistor
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
Δ−VDET
ΔTa
[mV/°C]^*1 = −VDET(S) (typ.)[V]^*2 ×
Δ−VDET
ΔTa • −VDET
[ppm/°C]^*3 ÷ 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
*5. The time period from when the pulse voltage of 6.0 V → −VDET(S) − 2.0 V or 0 V is applied to the SENSE pin to when
VOUT reaches VDD / 2.
*6. The time period from when the pulse voltage of 0.95 V → 10.0 V is applied to the SENSE pin to when VOUT reaches
VDD × 90%.
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