S-808XXC Datasheet, PDF (22/58 Pages) Seiko Instruments Inc – SUPER-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR

SUPER-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR
S-808xxC Series
Rev.4.3_00
„ Operation
1. Basic Operation: CMOS Output (Active Low)
1-1. When the power supply voltage (V_DD) is higher than the release voltage (+V_DET), the Nch transistor is
OFF and the Pch transistor is ON to provide V_DD (high) at the output. Since the Nch transistor N1 in
Figure 17 is OFF, the comparator input voltage is ^{(RB + RC) • VDD} .
RA + RB + RC
1-2. When the V_DD goes below +V_DET, the output provides the V_DD level, as long as the V_DD remains above
the detection voltage −V_DET. When the V_DD falls below −V_DET (point A in Figure 18), the Nch transistor
becomes ON, the Pch transistor becomes OFF, and the V_SS level appears at the output. At this time
the Nch transistor N1 in Figure 17 becomes ON, the comparator input voltage is changed to
RB • VDD _.
RA + RB
1-3. When the V_DD falls below the minimum operating voltage, the output becomes undefined, or goes to the
V_DD when the output is pulled up to the V_DD.
1-4. The V_SS level appears when the V_DD rises above the minimum operating voltage. The V_SS level still
appears even when the V_DD surpasses −V_DET, as long as it does not exceed the release voltage +V_DET.
1-5. When the V_DD rises above +V_DET (point B in Figure 18), the Nch transistor becomes OFF and the Pch
transistor becomes ON to provide V_DD level at the output.
VDD
−
*1
R_A
+
VSS
R_B
V_REF
R_C
N1
*1. Parasiteic diode
Figure 17 Operation 1
Pch
Nch
*1
OUT
*1
22
Seiko Instruments Inc.