S-1740 Datasheet, PDF (22/47 Pages) ABLIC Inc. – 5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT

POWER MONITORING OUTPUT, 5.5 V INPUT, 100 mA CMOS VOLTAGE REGULATOR WITH 0.5 μA SUPER LOW CURRENT CONSUMPTION
S-1740/1741 Series
Rev.1.1_00
 Precautions
• Generally, when a voltage regulator is used under the condition that the load current value is small (1.0 μA or less), the
output voltage may increase due to the leakage current of an output transistor.
• Generally, when a voltage regulator is used under the condition that the temperature is high, the output voltage may
increase due to the leakage current of an output transistor.
• Generally, when a voltage regulator is used under the condition that the impedance of the power supply is high, an
oscillation may occur. Perform thorough evaluation including the temperature characteristics with an actual application
to select C_IN.
• Generally, in a voltage regulator, an oscillation may occur depending on the selection of the external parts. The
following use conditions are recommended in the S-1740/1741 Series, however, perform thorough evaluation including
the temperature characteristics with an actual application to select C_IN, C_L and C_PM.
Input capacitor (C_IN):
Output capacitor (C_L):
Output capacitor (C_PM):
A ceramic capacitor with capacitance of 1.0 μF or more is recommended.
A ceramic capacitor with capacitance of 1.0 μF to 100 μF is recommended.
A ceramic capacitor with capacitance of 100 nF to 220 nF is recommended.
• Generally, in a voltage regulator, the values of an overshoot and an undershoot in the output voltage vary depending
on the variation factors of input voltage start-up, input voltage fluctuation and load fluctuation etc., or the capacitance of
C_IN, C_L or C_PM and the value of the equivalent series resistance (ESR), which may cause a problem to the stable
operation. Perform thorough evaluation including the temperature characteristics with an actual application to select
C_IN, C_L and C_PM.
• Generally, in a voltage regulator, if the VOUT pin is steeply shorted with GND, a negative voltage exceeding the
absolute maximum ratings may occur in the VOUT pin due to resonance phenomenon of the inductance and the
capacitance including C_L on the application. The resonance phenomenon is expected to be weakened by inserting a
series resistor into the resonance path, and the negative voltage is expected to be limited by inserting a protection
diode between the VOUT pin and the VSS pin.
• Make sure of the conditions for the input voltage, output voltage and the load current so that the internal loss does not
exceed the power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• When considering the output current value that the IC is able to output, make sure of the output current value specified
in Table 14 in " Electrical Characteristics" and footnote *5 of the table.
• Wiring patterns on the application related to the VIN pin, the VOUT pin and the VSS pin should be designed so that the
impedance is low. When mounting C_IN between the VIN pin and the VSS pin and C_L between the VOUT pin and the
VSS pin, connect the capacitors as close as possible to the respective destination pins of the IC.
• In the package equipped with heat sink of backside, mount the heat sink firmly. Since the heat radiation differs
according to the condition of the application, perform thorough evaluation with an actual application to confirm no
problems happen.
• SII Semiconductor Corporation claims no responsibility for any disputes arising out of or in connection with any
infringement by products including this IC of patents owned by a third party.
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