S-1740 Datasheet, PDF (20/47 Pages) ABLIC Inc. – 5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT

POWER MONITORING OUTPUT, 5.5 V INPUT, 100 mA CMOS VOLTAGE REGULATOR WITH 0.5 μA SUPER LOW CURRENT CONSUMPTION
S-1740/1741 Series
Rev.1.1_00
2. 3 PMEN pin voltage and output voltage (V_PMOUT)
2. 3. 1 S-1740/1741 Series A / C type
Figure 19 shows the relation between the PMEN pin voltage and the power monitoring output.
When "H" is input to the PMEN pin in the S-1740/1741 Series A type, or "L" is input to the PMEN pin in the C
type, the power monitoring output is enabled. Once power-up time (t_PU) = 10 ms max.^*1 elapses, the output
voltage (V_PMOUT) will settle and the power supply voltage can be monitored.
When "L" is input to the PMEN pin in the S-1740/1741 Series A type, or "H" is input to the PMEN pin in the C
type, the power monitoring output is disabled. V_PMOUT is set to the V_SS level by the built-in N-channel transistor.
By inputting "H" and "L" alternately to the PMEN pin, allowing for minimization of current consumption during
the period when the power supply voltage is not monitored.
*1. When Ta = +25°C, V_IN = 3.6 V, C_PM = 220 nF, no load
Example of active "H"
V_PMEN
V_PMOUT
t_PU
V_PMOUT(S) + V_POF
t_PU
V_PMOUT(S) + V_POF
Remark V_PMEN = V_IN ↔ V_SS
Figure 19
20