S-1740 Datasheet, PDF (16/47 Pages) ABLIC Inc. – 5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT

POWER MONITORING OUTPUT, 5.5 V INPUT, 100 mA CMOS VOLTAGE REGULATOR WITH 0.5 μA SUPER LOW CURRENT CONSUMPTION
S-1740/1741 Series
Rev.1.1_00
2. Power monitor block
2. 1 Power monitoring output
This is a function that divides the input voltage (V_IN) of the regulator into V_IN/2 or V_IN/3 and outputs the voltage.
For example, a microcontroller can monitor a battery voltage by inputting output voltage (V_PMOUT) to the microcontroller
A/D converter.
2. 2 Output voltage (V_PMOUT)
This is the voltage of the divided V_IN, which is V_IN/2 in the S-1740 Series and V_IN/3 in the S-1741 Series.
2. 3 Output offset voltage (V_POF)
This is the power monitor block offset voltage when V_IN, the load current and the temperature are in a certain
condition.
Caution If the certain condition is not satisfied, the output voltage may exceed the accuracy range of
±30 mV. Refer to " Electrical Characteristics" for details.
2. 4 Output impedance (R_PS)
This is the power monitor block impedance. It shows how much V_PMOUT changes when the load current changes.
For example, the output impedance can be used in sampling rate calculation as signal source impedance when
V_PMOUT from the PMOUT pin is input to the A/D converter as a microcontroller input signal.
2. 5 Power-up time (t_PU) (S-1740/1741 Series A / C type)
This is the time from when the power monitoring output is enabled until V_PMOUT stabilizes.
V_PMOUT, V_POF and R_PS are not guaranteed until the power-up time elapses.
2. 6 "L" output Nch ON resistance (R_PLOW) (S-1740/1741 Series A / C type)
The ON resistance of the N-channel transistor built into the power monitor block.
When the power monitoring output is disabled, V_PMOUT is set to the V_SS level by the built-in N-channel transistor.
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