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| S1009 Datasheet, PDF (12/43 Pages) Seiko Instruments Inc – SUPER-LOW CURRENT CONSUMPTION SUPER HIGH-ACCURACY VOLTAGE | |||
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SUPER-LOW CURRENT CONSUMPTION SUPER HIGH-ACCURACY VOLTAGE DETECTOR WITH DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
S-1009 Series
Rev.5.1_00
 Operation
1. Basic operation: CMOS output (active "L") product
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or more, the Nch transistor is OFF and
the Pch transistor is ON to output VDD ("H"). Since the Nch transistor N1 in Figure 14 is OFF, the comparator
input voltage is
(RB + RC ) ⢠VDD
RA + RB + RC
.
(2) Although VDD decreases to +VDET or less, VDD is output when VDD is the detection voltage (âVDET) or more.
When VDD decreases to âVDET or less (point A in Figure 15), the Nch transistor is ON and the Pch transistor
is OFF so that VSS is output. At this time, the Nch transistor N1 in Figure 14 is turned on, and the input
voltage to the comparator is
RB ⢠VDD
RA + RB
.
(3) The output is indefinite by decreasing VDD to the ICâs minimum operation voltage or less. If the output is
pulled up, it will be VDD.
(4) VSS is output by increasing VDD to the minimum operation voltage or more. Although VDD exceeds âVDET and
VDD is less than +VDET, the output is VSS.
(5) When increasing VDD to +VDET or more (point B in Figure 15), the Nch transistor is OFF and the Pch
transistor is ON so that VDD is output. At this time, VDD is output from the OUT pin after the passage of the
delay time (tD).
VDD
VSS
RA
*1
RB
VREF
RC
+
â
N1
Delay Pch
circuit
Nch
*1
CD
CD
*1
OUT
*1
*1. Parasiteic diode
Figure 14 Operation 1
(1) (2) (3) (4)
B
Hysteresis width
A
(VHYS)
(5)
VDD
Release voltage (+VDET)
Detection voltage (âVDET)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
tD
Figure 15 Operation 2
12
Seiko Instruments Inc.
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