S-19100N12H-M5T2U Datasheet, PDF (12/45 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT

FOR AUTOMOTIVE 105°C OPERATION VOLTAGE DETECTOR BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
S-19100xxxH Series
Rev.2.0_01
 Operation
1. Basic operation: CMOS output (active "L") product
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or higher, the Nch transistor is turned off
and the Pch transistor is turned on to output VDD ("H"). Since the Nch transistor N1 in Figure 13 is turned off,
the input voltage to the comparator is
(RB + RC ) •
RA + RB +
VDD
RC
.
(2) Even if VDD decreases to +VDET or lower, VDD is output when VDD is higher than the detection voltage (−VDET).
When VDD decreases to −VDET (point A in Figure 14) or lower, the Nch transistor is turned on and the Pch
transistor is turned off, and then VSS ("L") is output. At this time, the Nch transistor N1 in Figure 13 is turned
on, and the input voltage to the comparator is
RB
RA
• VDD
+ RB
.
(3) The output is unstable if VDD further decreases to the IC's minimum operation voltage or lower, and the
output is VDD when the output is pulled up.
(4) VSS is output when VDD increases to the minimum operation voltage or higher. Even if VDD exceeds −VDET, the
output is VSS when VDD is lower than +VDET.
(5) When VDD increases to +VDET (point B in Figure 14) or higher, the Nch transistor is turned off and the Pch
transistor is turned on, and then VDD is output. At this time, VDD is output from the OUT pin after the elapse of
the delay time (tD).
VDD
VSS
R_A
*1
R_B
V_REF
R_C
+
−
N1
Delay _Pch
circuit
Nch
*1
CD
C_D
*1
OUT
*1
*1. Parasitic diode
Figure 13 Operation 1
(1) (2) (3) (4)
B
Hysteresis width
A
(V_HYS)
(5)
V_DD
Release voltage (+V_DET)
Detection voltage (−V_DET)
Minimum operation voltage
VSS
V_DD
Output from OUT pin
V_SS
t_D
Figure 14 Operation 2
12