PEB20534 Datasheet, PDF (94/442 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

PEB 20534
DMA Controller and Central FIFOs
5.2.5 DMAC Performance
The DMAC supports linear bursting of multiple DWORDs for transfers of both data and
descriptors:
• On descriptor reads: 3 (Tx) / 3 (Rx) DWORDs at a time.
• On data write/read transactions for full scatter/gather sections up to 15 DWORDs at a
time.
The burst size for transmit data is determined by:
• the central transmit FIFO partition and threshold configurations (channel specific)
• the microprocessor interface arbitration and latency
The burst size for receive data is determined by:
• the central receive FIFO threshold configuration
• the SCC receive FIFO threshold
(Only DWORDs stored in consecutive sub-sections of the central receive FIFO can be
transferred to the host memory by one burst transfer. If the SCC receive FIFO
threshold is below 15 DWORDs (60 bytes) the consecutive sub-sections in the central
receive FIFO might be smaller as well depending on other channels activity. In this
case burst transfers of receive data might be limited to the SCC receive threshold
value.)
• the microprocessor interface arbitration and latency
In PCI mode up to 15 DWORDs bursts are supported. In de-multiplexed bus interface
mode the burst size is limited to 4 DWORDs or burst transactions are suppressed at all.
The DSCC4 DMAC uses PCI (fast) back-to-back transfers to achieve a maximum
throughput within one bus arbitration phase.
Semiconductor Group
94
Data Sheet 09.98