PEB20534 Datasheet, PDF (215/442 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

PEB 20534
Reset and Initialization Procedure
Table 37 Register Initialization for HDLC Transparent Mode 0, Test Loop
Register
Access
<= (write)
=> (read)
Value
Meaning
GMODE
<=
0000 0000
RESET Value:
- DMAC is controlled by HOLD bit
- Little Endian
- Default Priority Scheme
- MFP configured as LBI (not needed in
this example)
IQLENR1
<=
0000 0000 RESET Value:
Size of ring buffers: 32 entries
IQLENR2
<=
0000 0000 RESET Value:
Size of ring buffers: 32 entries
IQSCC1RXBAR <=
0000 2000 IQ Base Address for SCC1,RX
IQSCC1TXBAR <=
0000 4000 IQ Base Address for SCC1,TX
IQCFGBAR
<=
0000 6000 IQ Base Address for CFG
FIFOCR1
<=
07C0 0000 max. possible buffer of TFIFO reserved
for SCC1: 124 32-bit words
FIFOCR2
<=
0040 0000
Watermark of TFIFO (SCC1 portion) is
set to 2 (example).
(As soon as less than two DWORDs are
in the central TFIFO buffer, the TFIFO
requests for more data.)
FIFOCR3
<=
0000 0000
RESET Value:
Watermark of RFIFO is set to one.
(As soon as one 32-bit word is stored in
the RFIFO, the RFIFO requests for data
transfer to shared memory.
FIFOCR4
<=
0000 0000
RESET Value:
Watermark of TFIFO forward threshold
(SCC1 portion) is set to one.
(As soon as at least one 32-bit word is in
the central TFIFO, the TFIFO transfers
data to SCC1 transmit FIFO.)
Semiconductor Group
215
Data Sheet 09.98