PEB20534 Datasheet, PDF (345/442 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

XON
XPR
BRK
BRKT
RDO
TCD
PEB 20534
Detailed Register Description
XON Character Detected Interrupt
(async mode)
ASYNC Mode:
This bit is set to ’1’, if the currently received character matched the XON
character programmed in bit field ’XON’ in register XNXF and indicates,
that the transmitter is switched to XON-state if in-band flow control is
enabled via bit ’FLON’ in register CCR2.
Transmit Pool Ready Interrupt
(all modes)
This bit is set to ’1’, if a transmitter reset command was executed
successfully (command bit ’XRES’ in register CMDR) and transmit data
can be written to the FIFO by the DMA controller.
A ’XPR’ interrupt is not generated, if no sufficient transmit clock is
available (depending on the selected clock mode).
Break Interrupt
(async mode)
This bit is set to ’1’, if a break condition was detected on the receive line,
i.e. a low level for a time equal to (character length + parity bit + stop
bit(s)) bits depending on the selected ASYNC character format.
Break Terminated Interrupt
(async mode)
This bit is set to ’1’, if a previously detected break condition on the
receive line is terminated by a low to high transition.
Receive Data Overflow Interrupt
(hdlc mode)
This bit is set to ’1’, if receive data of the current frame got lost because
of a SCC receive FIFO full condition. However the rest of the frame is
received and discarded as long as the receive FIFO remains full and is
stored as soon as FIFO space is available again. The receive status byte
(RSTA) of such a frame contains an ’RDO’ indication.
Termination Character Detected Interrupt (async/bisync modes)
This bit is set to ’1’, if a termination character is detected in the receive
data stream. The SCC will insert a ’frame end / block end’ indication to
the SCC receive FIFO which causes the DMAC to finish the current
receive descriptor.
Semiconductor Group
345
Data Sheet 09.98