PEB20534 Datasheet, PDF (247/442 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

PEB 20534
Detailed Register Description
Table 47 IQLENR1: Interrupt Queue Length Register 1
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
read/write
0000 000_H
000C_H
written by CPU
evaluated by DSCC4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Interrupt Queues Length Configuration
IQSCC0RXLEN
IQSCC1RXLEN
IQSCC2RXLEN
IQSCC3RXLEN
Bit 15 14 13 12 11 10 9 8 7 6 5 4
Interrupt Queues Length Configuration
IQSCC0TXLEN
IQSCC1TXLEN
IQSCC2TXLEN
3210
IQSCC3TXLEN
Semiconductor Group
247
Data Sheet 09.98