PEB20534 Datasheet, PDF (269/442 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

PEB 20534
Detailed Register Description
CHiLRDA
i = 3...0
(RX Channel 3...0)
These registers determine the last descriptor address of the channel
specific receive descriptor chain and can be located anywhere in the 32
bit address range. The last descriptor address is written by the CPU and
marks the corresponding descriptor as the last descriptor in the receive
descriptor chain.
After write access to one of these registers, the DMA controller again
compares the first (current) receive descriptor address (register
CHiFRDA) with the last descriptor address (register CHiLRDA), if the
corresponding DMA controller channel was in internal HOLD state. If
these addresses do not match any more, the DMA channel leaves the
internal HOLD state, re-reads the next descriptor address of the current
receive descriptor and continues operation.
These registers are only valid, if the DMA controller is operating in Last
Descriptor Address Mode (bit CMODE set to ’1’ in register GMODE).
Note: The last descriptor addresses must be 32-bit aligned, i.e. bit 1 and
0 must be set to ’0’.
Semiconductor Group
269
Data Sheet 09.98