SLX24C32 Datasheet, PDF(9/26 Page) Siemens Semiconductor Group – 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

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SLX24C32 Datasheet, PDF (9/26 Pages) Siemens Semiconductor Group – 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

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SLx 24C32

Device Addressing and EEPROM Addressing

After a START condition, the master always transmits a command byte CSW or CSR.

After the acknowledge of the EEPROM control bytes follow, their contents and the

transmitter depend on the previous command byte. The description of the command and

control bytes is shown in table 2.

Command Byte

Control Bytes

Selects one of the 8 addressable slave devices: The chip select

bits CS2, CS1 and CS0 (bit positions b3 to b1) are compared to their

corresponding hard wired input pins CS2, CS1 and CS0,

respectively.

Selects operation: the least significant bit b0 is low for a write

operation (Chip Select Write Command Byte, CSW) or set high for

a read operation (Chip Select Read Command Byte, CSR).

Following CSW (b0 = 0): The address bytes AHI/ALO containing

the address bits A0 to A11 are transmitted by the master.

Following CSR (b0 = 1): The EEPROM transmits the read out data.

EEPROM data are read as long as the master pulls down SDA after

each byte in order to acknowledge the transfer. The read operation

is stopped by the master by releasing SDA (no acknowledge is

applied) followed by a STOP condition.

Table 2

Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM

Command

CSW

CSR

AHI

ALO

DATA

Definition

Function

b7 b6 b5 b4 b3 b2 b1 b0

1 0 1 0 CS2 CS1 CS0 0 chip select for write

1 0 1 0 CS2 CS1 CS0 1 chip select for read

0 0 0 0 A11 A10 A9 A8 high address

A7 A6 A5 A4 A3 A2 A1 A0 low address

D7 D6 D5 D4 D3 D2 D1 D0 data byte

The device has an internal address counter which points to the current EEPROM

address.

The address counter is incremented

â after a data byte to be written has been acknowledged, during entry of further data

byte

â during a byte read, thus the address counter points to the following address after

reading a data byte.

The timing conventions for read and write operations are described in figures 5 and 6.

Semiconductor Group

Preliminary 1998-07-27

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