SLX24C32 Datasheet, PDF (13/26 Pages) Siemens Semiconductor Group – 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C32
The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for
speed enhancement in order to detect the end of the erase/write cycle. Please refer to
chapter 5.3, Acknowledge Polling for further information.
5.3 Acknowledge Polling
During the erase/write cycle the EEPROM will not respond to a new command byte until
the internal write procedure is completed. At the end of active programming the chip
returns to the standby mode and the last entered EEPROM byte remains addressed by
the address counter. To determine the end of the internal erase/write cycle acknowledge
polling can be initiated by the master by sending a START condition followed by a
command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/
write cycle is not completed, the device will not acknowledge the transmission. If the
internal erase/write cycle is completed, the device acknowledges the received command
byte and the protocol activities can continue.
Internal Programming
Procedure
Send Start
Send CS-Byte
Acknowledge
from EEPROM
received?
Yes
Next Operation
No
IED02131
Figure 9
Flow Chart “Acknowledge Polling”
Semiconductor Group
13
Preliminary 1998-07-27