SLX24C32 Datasheet, PDF (18/26 Pages) Siemens Semiconductor Group – 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C32
7
Page Protection Mode^TM
The page protection mode is supported by the SLx 24C32.../P types only. For example
SLA 24C32-D/P has the same functionality as SLA 24C32-D enhanced by page
protection mode.
Each page (32 bytes) in the data memory can be protected against unintended data
changes by an associated protection bit. The protection bit memory consists of an
additional EEPROM of 128 bit (figure 14).
Data in the data memory can be modified only if the assigned protection bit is erased
(logical state “1”). After writing the data bytes to a page, the protection is achieved by
writing the associated protection bit (logical state “0”). Further changes in the data in a
protected page is possible only after erasing the protection bit.
Page 0
Page 1
Page 2
Page 3
...
Page n 0 1 2 3
Data Memory Area
...
...
Byte
0
1
2
3
...
31 ⁿ
Bit
IED02521
Figure 14
Data Page and Assigned Protection Memory
A special procedure to write or erase a protection bit guarantees proper activation or
deactivation of page protection. For protection bit write or erase all 32 data bytes of the
respective page have to be entered for verification. The data then are compared
internally with the data to be protected. In case of identity the protection bit is written or
erased respectively.
Semiconductor Group
18
Preliminary 1998-07-27