SLX24C32 Datasheet, PDF (11/26 Pages) Siemens Semiconductor Group – 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C32
5
Write Operations
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one
programming procedure. Setting the Write Protection pin WP to V_CC activates the
hardware write protection and therefore any programming is suppressed. For normal
operation WP has to be set to V_SS.
5.1 Byte Write
Address Setting
Transmission of Data
Programming Cycle
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following two bytes AHI/ALO
with the EEPROM address (A0 to A11) are loaded into the
address counter of the EEPROM and acknowledged by the
EEPROM.
Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the bytes AHI (A8 to A11)
and ALO (A0 to A7). The programming procedure consists of
an internally timed erase/write cycle. In the first step, the
selected byte is erased to “1”. With the next internal step, the
addressed byte is written according to the contents of the
buffer.
S
T
S
Bus Activity ^A Command Byte EEPROM Address EEPROM Address Data Byte
T
Master
R
CSW
AHI
ALO
O
T
P
SDA Line S
0
P
Bus Activity
EEPROM
A
A
A
A
C
C
C
C
K
K
K
K
IED02518
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for
speed enhancement in order to detect the end of the erase/write cycle. Please refer to
chapter 5.3, Acknowledge Polling for further information.
Semiconductor Group
11
Preliminary 1998-07-27