SLX24C32 Datasheet, PDF (20/26 Pages) Siemens Semiconductor Group – 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C32
7.2 Protection Bit Write and Erase
For writing or erasing a protection bit the data of the respective page have to be known
by the master. The master has to present the page data as a reference for comparison
by the EEPROM. A successful comparison is necessary in order to change the value of
the protection bit.
The data of the page are not affected by the write or erase procedure of the protection
bit. The I²C-Bus protocol is shown in figure 15 for protection bit write and figure 16 for
protection bit erase.
Bus
Activity
Master
S
T Command
A Byte
R _CSW
T
EEPROM
Address
AHI
EEPROM
Address
ALO
S
T Command
A Byte
R _CSW
T
Control
Byte
CTW
Data
Byte n
Data _... Data S
Byte n+1 Byte n+31 T
O
P
SDA Line S
0
00000 S
0
01
P
Bus Activity
EEPROM
A
A
A
C
C
C
K
K
K
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
IED02522
Figure 15
Sequence for Protection Bit Write
Bus
Activity
Master
S
T Command
A Byte
R _CSW
T
EEPROM
Address
AHI
EEPROM
Address
ALO
S
T Command
A Byte
R _CSW
T
Control
Byte
CTE
Data
Byte n
Data
Byte n+1
Data S
Byte n+31 T
O
P
SDA Line S
0
00000 S
0
11
P
Bus Activity
EEPROM
A
A
A
C
C
C
K
K
K
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
IED02523
Figure 16
Sequence for Protection Bit Erase
The first command byte CSW followed by the address bytes AHI/ALO determines the
page to be protected. The second command byte CSW (identical content of first CSW)
is followed by the control byte CTW = 01_H for protection bit write or CTE = 03_H for
protection bit erase. Depending on CTx, the addressed protection bit will be either
written or erased.
The control byte CTx is followed by 32 parameter bytes identical to the 32 data bytes of
the page to be protected or unprotected. The data of the first entered byte must be
identical to the data byte stored at the lowest address of the current page. The other
Semiconductor Group
20
Preliminary 1998-07-27