SLX24C32 Datasheet, PDF (15/26 Pages) Siemens Semiconductor Group – 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C32
6
Read Operations
Reading of the EEPROM data is initiated by the Master with the command byte CSR.
6.1 Random Read
Random read operations allow the master to access any memory location.
Address Setting
Transmission of CSR
Transmission of
EEPROM Data
STOP Condition from
Master
The master generates a START condition followed by the
command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low state on the SDA
line. Now the master transmits the EEPROM address (AHI/
ALO) to the EEPROM and the internal address counter is
loaded with the desired address.
After the acknowledge for the EEPROM address is received,
the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter by one
byte.
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
S
S
T
T
S
Bus Activity ^A Command Byte EEPROM Address EEPROM Address ^A Command Byte
T
Master
R
CSW
AHI
ALO
R
CSR
O
T
T
P
SDA Line S
0
S
1
P
Bus Activity
EEPROM
A
A
A
C
C
C
K
K
K
A Data Byte
C
K
IED02520
Figure 11
Random Read
Semiconductor Group
15
Preliminary 1998-07-27