SDA9205-2 Datasheet, PDF (8/31 Pages) Siemens Semiconductor Group – Triple 8-Bit Analog-to-Digital-Converter

SDA 9205-2
The following DSP functions are available
(1.0)
(1.1)
α_n = a_{n – 3}
α_n = 1/2 (a_{n – 4} + a_{n – 3})
n = sampling point
ADC A
(2.0)
(2.1)
(2.2)
(2.3)
β_n = b_{n – 3}
β_n = 1/2 (b_{n – 4} + b_{n – 3})
β_4n = 1/4 (b_{4n – 5} + b_{4n – 4} + b_{4n – 3} + b_{4n – 2n}), β_{4n – 3,2,1}
β_8n = 1/8 (b_{8n – 7} + b_{8n – 6} + ..... + b_8n), β_{8n – 7,6,5,4,3,2,1}
ADC B
arbitrarily
arbitrarily
(2.0)
(2.1)
(2.2)
(2.3)
γ_n = c_{n – 3}
γ_n = 1/2 (c_{n – 4} + c_{n – 3})
γ_4n = 1/4 (c_{4n – 5} + c_{4n – 4} + c_{4n – 3} + c_{4n – 2})
γ_8n = 1/8 (c_{8n – 7} + c_{8n – 6} + ..... + c_8n)
γ_{4n – 3,2,1}
γ_{8n – 7,6,5,4,3,2,1}
ADC C
arbitrarily
arbitrarily
Averaged results are rounded to eight bits (X ≤ 0.5 → 0; X > 0.5 → 1)
A group delay of 0.5 CLK cycles exists between DSP (1.0, 2.0) and the other DSP functions.
Semiconductor Group
8