SDA9205-2 Datasheet, PDF (26/31 Pages) Siemens Semiconductor Group – Triple 8-Bit Analog-to-Digital-Converter

SDA 9205-2
Sample output data-delay is shown on format 8:8:8 with DSP function 1.0 + 2.0
Figure 6
Diagram of Complete Timing
There is a delay of 9 clock cycles between sampling of an analog input signal and the corresponding
digital output signal.
Semiconductor Group
26