SDA9205-2 Datasheet, PDF (11/31 Pages) Siemens Semiconductor Group – Triple 8-Bit Analog-to-Digital-Converter

SDA 9205-2
The digital output data are synchronized by the FSY signal. The first high of FSY defines the first
output format byte and is synchronized to CLK. In case of asynchronism the first (in formats 8:1:1,
4:1:1 the first and the second) output format byte after FSY had gone high does not contain valid
data. Timing of FSY, CLK and output data is shown in figure 4 with output format 4:1:1.
Figure 4
Semiconductor Group
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