SDA9205-2 Datasheet, PDF (20/31 Pages) Siemens Semiconductor Group – Triple 8-Bit Analog-to-Digital-Converter

SDA 9205-2
Output Coding for Binary/Two’s Complement Mode
Binary or two’s complement output coding is selectable for each separate output port (A, B, C) via
control inputs DTA, DTB, DTC. This coding is independent from selected formats (8:8:8, 8:4:4,
8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1).
Table 1
Output Coding for Formats 8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1
Table 1 is valid for V_REFL = 0.5 V and V_REFH = 2.5 V
Step
VIN
Converter
A
Underflow
0
1
.
.
.
.
254
255
Overflow
< V_CA – 0.125 V
V_CA – 0.125 V
V_CA – 0.117 V
.
.
.
.
V_CA + 1.867 V
V_CA + 1.875 V
> V_CA + 1.875 V
VIN
Converter
B, C
OFL UFL Binary
Bit Bit Output
76543210
< V_{CB, C} – 1 V
0 1 00000000
V_{CB, C} – 1 V
0 0 00000000
V_{CB, C} – 0.992 V 0
0
00000001
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
V_{CB, C} + 0.992 V .
.
11111110
V_{CB, C} + 1 V
0 0 11111111
> V_{CB, C} + 1 V
1 0 11111111
Two’s
Complement
76543210
10000000
10000000
10000001
.
.
.
.
01111110
01111111
01111111
V_CA = ext. clamping level during CLAMP high pulse at C_{ext cl} on channel AINA.
V_{CB, C} = ext. clamping level during CLAMP high pulse at C_{ext cl} on channel AINB and AINC.
In output format 4:2:2 a special suppression of code 0 and code 255 is provided in the binary output
mode.
Semiconductor Group
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