SDA9205-2 Datasheet, PDF (21/31 Pages) Siemens Semiconductor Group – Triple 8-Bit Analog-to-Digital-Converter

SDA 9205-2
Table 2
Output Coding for Format 4:2:2
Table 2 is valid for V_REFL = 0.5 V and V_REFH = 2.5 V
Step
VIN
Converter
A
Underflow
0
1
2
.
.
253
254
255
Overflow
< V_CA – 0.125 V
V_CA – 0.125 V
V_CA – 0.117 V
.
.
.
.
V_CA + 1.867 V
V_CA + 1.875 V
> V_CA + 1.875 V
VIN
Converter
B, C
OFL UFL Binary
Bit Bit Output
76543210
< V_{CB, C} – 1 V
0 1 00000001
V_{CB, C} – 1 V
0 0 00000001
V_{CB, C} – 0.992 V 0
0
00000001
.
0.
00000010
.
.
.
.
.
.
.
.
.
0 0 11111101
V_{CB, C} + 0.992 V 0
0
11111110
V_{CB, C} + 1 V
0 0 11111110
> V_{CB, C} + 1 V
1 0 11111110
Two’s
Complement
76543210
10000000
10000000
10000001
10000010
V_CA = ext. clamping level during CLAMP high pulse at C_{ext cl} on channel AINA.
V_{CB, C} = ext. clamping level during CLAMP high pulse at C_{ext cl} on channel AINB and AINC.
Semiconductor Group
21