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SDA9205-2 Datasheet, PDF (6/31 Pages) Siemens Semiconductor Group – Triple 8-Bit Analog-to-Digital-Converter
SDA 9205-2
The external clamping capacitance is loaded by on chip current sources (typ. 200 µA) during
clamping. So the loading time depends on the values of Cext cl.
The loading time for a complete loading cycle is 1200 CLK pulses typical (44 µs with 27 MHz CLK
and Cext cl = 10 nF) as shown in figure 1.
Cext cl = 10 nF, RS = 50 Ω
Figure 1
Typical Clamp Timing Diagram
Semiconductor Group
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