HYS6472V4200GU Datasheet, PDF (8/15 Pages) Siemens Semiconductor Group – 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module

HYS64(72)V4200/8220GU
SDRAM-Modules
AC Characteristics 3)4)
T_A = 0 to 70 °C; V_SS = 0 V; V_CC = 3.3 V ± 0.3 V, t_T = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-8
-8B
PC100-222 PC100-323
-10
PC66
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
t_CK
CAS Latency = 3
CAS Latency = 2
System Frequency
f_CK
CAS Latency = 3
CAS Latency = 2
Clock Access Time
t_AC
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Input Setup time
Input Hold Time
CKE Setup Time
(Power down mode)
t_CH
t_CL
t_CS
t_CH
t_CKSP
CKE Setup Time
(Self Refresh Exit)
t_CKSR
Transition time (rise and fall)
t_T
10 – 10 – 10 – ns
10 – 12 – 15 – ns
– 100 – 100 – 100 MHz
– 100 – 83 – 66 MHz
–
6
–
6
–
8 ns ^4,5)
–
6
–
7
–
9 ns
3
–
3
– 3.5 – ns 6)
3
–
3
– 3.5 – ns 6)
2
–
2
–
3
– ns 7)
1
–
1
–
1
– ns 7)
2.5 – 2.5 –
3
– ns 8)
8
– 10 –
8
– ns 9)
1
–
1
–
1
– ns
Common Parameters
RAS to CAS delay
t_RCD
Precharge Time
t_RP
Active Command Period
t_RAS
Cycle Time
t_RC
Bank to Bank Delay Time
t_RRD
CAS to CAS delay time (same t_CCD
bank)
20 – 20 – 30 – ns
20 – 30 – 30 – ns
50 100k 60 100k 70 100k ns
70 – 80 – 80 – ns
16 – 20 – 20 – ns
1
–
1
–
1
– CLK
Semiconductor Group
8